Conference: Automated Tiny Neural Network design with MCU constraints
Tiny Machine Learning (TinyML) is a growing, widely attended community focusing on the deployment of Deep Learning (DL) models on Micro-Controller Units (MCUs).
Running a trained DL model on a MCU requires the capability to hand craft the network topology and associated hyperparameters to fit hardware requirements, such as operating frequency in the range of 10s-100s MHz, embedded Flash memory in the range of 100s KB to MBs and embedded SRAM in the range of 10s of KB to MBs, with associated power consumption of 100s mW or less.
Unfortunately, a hand crafted design methodology poses multiple challenges:
AI and embedded developers exhibit different orthogonal skills, which do not meet each other during the development of AI applications till the validation in an operational environment
Tools for automated network design often assume virtually unlimited resources (typically deep networks are trained on the cloud or GPU-based systems)
The time-to-market from conception to realization of an AI system is usually quite long. Consequently, mass market adoption of AI technologies at the deep edge is quite jeopardized.
We propose to start from a neural network “template” and automatically optimize its hyperparameters while assuring its deployment on a given MCU, such as STM32 or Chorus SPC58.
Our solution is based on Sequential Model Based Optimization (SMBO) – aka Bayesian Optimization (BO) – that is the standard methodology for Automated Machine Learning (AutoML) and Neural Architecture Search (NAS).
Although AutoML and NAS are successfully applied on large GPU/Cloud platforms (i.e., some AutoML/NAS tools are commercialized by Google, Amazon and Microsoft), their application is still an issue in the case of tiny devices, such as MCUs.
Our approach, instead, includes “deployability” constraints – relatively to hardware resources of the MCUs – into the hyperparameter optimization process, leading to the new “AutoTinyML” perspective.
This talk will present our approach, along with pros and cons with respect to multi-objective optimization (usually adopted to reduce resource usage on cloud). A set of relevant results will be presented and discussed, providing an overview on the next open challenges and perspectives in the AutoTinyML field.
One year before graduating from the Polytechnic University of Milan in 1992, Danilo Pau joined STMicroelectronics, where he worked on HDMAC and MPEG2 video memory reduction, video coding, embedded graphics, and computer vision. Today, his work focuses on developing solutions for deep learning tools and applications.
Since 2019 Danilo is an IEEE Fellow, serves as Industry Ambassador coordinator for IEEE Region 8 South Europe, vice-chairman of the “Intelligent Cyber-Physical Systems” Task Force within IEEE CIS, and Member of the Machine Learning, Deep Learning and AI in the CE (MDA) Technical Stream Committee IEEE Consumer Electronics Society (CESoc).
With over 80 patents, 94 publications, 113 MPEG authored documents and more than 31 invited talks/seminars at various worldwide Universities and Conferences, Danilo's favorite activity remains mentoring undergraduate students, MSc engineers and PhD students from various universities in Italy, US, France and India.
To attend this conference, please liaise with your ICAIR coordinator